1. Field of the Invention
This invention relates to a memory device and, more particularly, to a memory device to write data to a memory cell according to a write enable signal and a data mask signal.
2. Description of the Related Art
There are memory devices which write data to memory cell according to a write enable signal and a data mask signal. These memory devices receive data in a buffer at a present cycle, and transfer and write the data in a subsequent cycle, according to the write enable signal and the data mask signal.
In such a memory device, it is necessary to prevent erroneous writing of data due to writing malfunction. There, a delay in a write operation also has to be avoided.
In a semiconductor memory device, when a write operation is externally directed in a last-second state of whether to perform writing or not, one of (1) not to perform writing, and (2) to perform writing and receive data or a masking state correctly, has to be executed. When performing the write operation, receiving of unwanted mask data which is being transferred, or writing of a prior data using another address without receiving new data, must be avoided. However, any measure to control occurrence of write commands results in a slow-down of a write operation and a write cycle.
Another conventional arts are also published in the following patent documents 1 to 3.
[Patent Document 1]
Japanese Patent Application Laid-open No. Hei 11-7770
[Patent Document 2]
Japanese Patent Application Laid-open No. 2003-7060
[Patent Document 3]
Japanese Patent Application Laid-open No. 2001-351377